library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity somador_subtrator is
	port(
	 	Su, Eu : in std_logic;
		A, B : in std_logic_vector(7 downto 0);
		S : out std_logic_vector(7 downto 0):="00000000"
	);
end somador_subtrator;

architecture arquitetura of somador_subtrator is
	signal tmp_S : std_logic_vector(7 downto 0):="00000000";
	signal soma, subtracao, not_B: std_logic_vector (7 downto 0):="00000000";
	
	component full_adder
      port (cin, a, b : in std_logic;
            f, cout : out std_logic
      );
   end component;

   component somador_8bits
      port (
      	cin : in std_logic;
	      a, b : in std_logic_vector(7 downto 0);
	      f: out std_logic_vector(7 downto 0)
	   );
   end component;
	
begin

   ADD: somador_8bits port map ('0', A, B, soma);
   not_B <= not B;
   SUB: somador_8bits port map ('1', A, not_B, subtracao);
   
	process (Su)
	begin
		if (Su='1') then
			tmp_S <= subtracao;
		else
			tmp_S <= soma;
		end if;
	end process;
	
	process (Eu)
	begin
		if(Eu='1') then
    	   S<=tmp_S;
      else
         S<="ZZZZZZZZ";
      end if;
	end process;
	
end arquitetura;
